1. Field of the Invention
The present invention is related to a printed wiring board in which a plated conductor or plated conductors are formed in penetrating-holes formed in an insulating material, and specifically to a printed wiring board having a plated conductor with improved conduction and a substrate with improved strength, and a method of producing such a printed wiring board.
2. Discussion of the Background
In a conventional printed wiring board, filled-type through-holes are formed by plating a metal in penetrating-holes formed in an insulating resin substrate. These filled-type through-holes are formed as plated through-holes for electrically connecting conductor circuits formed on the front and back surfaces of the insulating resin substrate in the printed wiring board.
For example, Japanese Unexamined Patent Publication No. 2004-311919 describes a method of forming through-holes. To form a through-hole, a penetrating-hole 2 is formed in an insulating resin substrate 1 as shown in FIG. 9 (a), and a seed layer 3 made of metal is formed by electroless plating on a surface of the insulating resin substrate 1, including the inner wall of the penetrating-hole 2 as shown in FIG. 9 (b). Then, electrolytic plating is performed to form an electrolytic plated layer 4 on the seed layer 3 as shown in FIG. 9 (c), and by further performing the electrolytic plating process, a through-hole 6 is formed by filling the penetrating-hole 2 with metal as shown in FIG. 9 (d). In a through-hole formed in such a method as shown in FIG. 9 (d), a void 8 is prone to be formed in its inside.
According to another method as shown in FIGS. 10 (a) to (b), a penetrating-hole 2 having a shape symmetrically tapering toward the midpoint of an insulating resin substrate 1 as shown in a vertical cross-section of FIG. 10(a) is formed in an insulating resin substrate 1, and a through-hole 6 is formed by filling metal into the penetrating-hole 2, i.e., by performing electroless plating to form a seed layer made of metal and an electrolytic plating process over the seed layer as shown in FIG. 10 (a) to (b).
The contents of the foregoing publication is incorporated herein by reference in their entirety.